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Network On Chip
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51	Route Packets, Not Wires: On-Chip Interconnection Networks William J. Dally and Brian Towles Computer Systems Laboratory Stanford University Stanford, CA 94305 {billd,btowles}@cva.stanford.edu Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:04 Computer networking Computer memory Ethernet Network switch Content-addressable memory Cell Wormhole switching Network On Chip Computing Electronic engineering Electronics
52	VLSI Micro-Architectures for High-Radix Crossbar Schedulers Giorgos Passas, Manolis Katevenis, Dionisios Pnevmatikatos presentation by Giorgos Passas FORTH & Univ. of Crete, Greece Add to Reading List Source URL: www.ics.forth.gr Language: English - Date: 2014-02-26 11:54:20 Network On Chip Scheduling Giorgos Electronics Scheduling algorithms Electronic engineering Electronic design automation
53	A Delay Model for Router Micro-architectures Li-Shiuan Peh William J. Dally Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:05 Network On Chip Routing Wormhole switching OSI protocols Throughput Router Network switch Forwarding plane Load-balanced switch Network architecture Computing Flow control
54	On-chip Communication and Synchronization Mechanisms with Cache-Integrated Network Interfaces Stamatis Kavadias, Manolis Katevenis ∗ Michail Zampetakis, Dimitrios S. Nikolopoulos Institute of Computer Science Add to Reading List Source URL: www.ics.forth.gr Language: English - Date: 2013-12-23 07:16:59 Scratchpad memory CPU cache Multi-core processor Parallel computing Remote direct memory access Stream processing Direct memory access LEON Cache Computer hardware Computing Computer memory
55	In Proceedings of the 6th International Symposium on High-Performance Computer Architecture, Toulouse, France, January 10-12, 2000. ppFlit-Reservation Flow Control Li-Shiuan Peh William J. Dally Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:05 Wormhole switching Computing OSI protocols Electronic engineering Network performance Streaming Throughput Latency Scheduling Flow control Network On Chip Routing
56	Stanford University Concurrent VLSI Architecture Memo 124 Elastic Buffer Networks-on-Chip George Michelogiannakis∗, James Balfour and William J. Dally Concurrent VLSI Architecture Group Computer Systems Laboratory Stan Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2008-08-26 22:57:32 Computing Router Network switch Hop count Throughput Network On Chip Transmission Control Protocol Wormhole switching Network architecture Routing Electronic engineering
57	In Proceedings of the 7th International Symposium on High-Performance Computer Architecture, Jan, 2001, Monterrey, Mexico, ppBest Student Paper Award) A Delay Model and Speculative Architecture for Pip Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:04 Flow control Network On Chip Routing Wormhole switching Network performance Throughput Network switch Router Traffic flow Network architecture Computing Electronic engineering
58	Approaching Ideal NoC Latency with Pre-Configured Routes George Michelogiannakis1, Dionisios Pnevmatikatos2 and Manolis Katevenis1 Institute of Computer Science (ICS) Foundation for Research & Technology - Hellas (FORTH) Add to Reading List Source URL: www.ics.forth.gr Language: English - Date: 2013-12-23 07:16:41 Routing Flow control Network On Chip Wormhole switching Computer networking Latency Hop FIFO Network switch Electronic engineering Computing Electronics
59	COUNCIL WORKING GROUP TO PREPARE FOR THE 2012 WORLD CONFERENCE ON INTERNATIONAL TELECOMMUNICATIONS GENEVA, 20-22 June 2012 Document CWG-WCIT12/C–104-E Add to Reading List Source URL: www.soumu.go.jp Language: English - Date: 2015-03-01 19:36:23 ITU-T CWG Network On Chip SMS Electronic engineering Technology Mobile technology
60	Explicit Communication and Synchronization in SARC Manolis G.H. Katevenis∗ , Vassilis Papaefstathiou∗ , Stamatis Kavadias∗ , Dionisios Pnevmatikatos∗ , Federico Silla+ , Dimitrios S. Nikolopoulos∗ ∗ Add to Reading List Source URL: www.ics.forth.gr Language: English - Date: 2013-12-23 07:16:58 Electronics Local area networks Remote direct memory access Parallel computing Scratchpad memory CPU cache Cache Prefetcher Network On Chip Computing Computer memory Computer hardware

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